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AS1538/as1540 8/4-channel, 12-bit i2c analog-to-digital converter data sheet www.austriamicrosystems.com revision 1.03 1 - 20 1 general description the AS1538/as1540 are single-supply, low-power, 12- bit data acquisition devices featuring a serial i2c inter- face and an 8-channel (AS1538) or 4-channel (as1540) multiplexer. the analog-to-digital (a/d) converters features a sam- ple-and-hold amplifier an internal asynchronous clock and an internal reference. the combination of an i 2 c serial, 2-wire interface and micropower consumption makes the AS1538 and as1540 ideal for applications requiring the a/d con- verter to be close to the input source in remote locations and for applications requiring isolation. the device is available in a tssop-16 or tqfn 4x4 16- pin package. figure 1. block diagram 2 key features single supply: 2.7 to 5.25v 8-channel multiplexer (AS1538) 4-channel multiplexer (as1540) sampling rate: 50ksps no missing codes internal reference: 2.5v high speed i 2 c interface at 3.4mhz <1.5a full shutdown current tssop-16 or tqfn 4x4 16-pin package 3 applications the device is ideal for voltage-supply monitoring, iso- lated data acquisition, transducer interfaces, battery- operated systems, remo te data acquisition or any other analog-to-digital conversion application. a0 scl ch0 sda AS1538/as1540 8-channel mux ch1 ch2 ch3 ch4 ch5 ch6 ch7 ref in/out sample/ hold amp successive approximation register cdac comparator serial interface a1 internal 2.5v reference buffer gnd com AS1538 only
www.austriamicrosystems.com revision 1.03 2 - 20 AS1538/as1540 data sheet - pinout 4 pinout pin assignments figure 2. pin assignments (top view) pin descriptions table 1. pin descriptions AS1538 as1540 pin name description - 1:3,16 ch0:ch3 analog input channels 0 to 3 1:8 - ch0:ch7 analog input channels 0 to 7 96gnd analog ground 10 7 ref in/out internal reference/exte rnal reference input 11 8 com analog input channel common 12 10 a0 slave address bit 0 13 11 a1 slave address bit 1 14 12 scl serial clock 15 13 sda serial data 16 15 +v dd power supply input . 2.7 to 5.25v. - 4, 5, 9, 14 nc not connected 10 ref in/out 3 ch2 2 ch1 1 ch0 16 +v dd AS1538 4 ch3 15 sda 12 a0 5 ch4 8 ch7 6 ch5 7 ch6 14 scl 13 a1 11 com 9gnd scl 13 6 12 a0 10 5 14 15 ch1 1 ch2 2 n/c 4 as1540 ch3 3 7 8 n/c 9 a1 11 16 n/c gnd com ref in/out sda n/c ch0 +v dd
www.austriamicrosystems.com revision 1.03 3 - 20 AS1538/as1540 data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the de vice at these or any other cond itions beyond those indicated in electrical character- istics on page 4 is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments +v dd to gnd -0.3 +6 v digital input voltage to gnd -0.3 +v dd + 0.3 v thermal resistance ja 100 c/w on pcb operating temperature range -40 +85 oc storage temperature range -65 +150 oc junction temperature (t jmax ) 150 oc esd 1.5 kv hbm mil-std. 883e 3015.7 methods package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020c ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn).
www.austriamicrosystems.com revision 1.03 4 - 20 AS1538/as1540 data sheet - electrical characteristics 6 electrical characteristics electrical characteristics +v dd = + 2.7 to +5.25v, v ref = + 2.5v external, scl = 3.4mhz, t amb = -40 to +85 oc (unless otherwise specified). table 3. electrical characteristics symbol parameter condition min typ max unit analog input fullscale input span positive input, negative input 0 v ref v absolute input range positive input -0.3 +v dd + 0.3 v negative input -0.3 +v dd + 0.3 v capacitance track mode 15 pf hold mode 8 i leak leakage current 0.1 1 a static performance no missing codes 12 bits integral linearity error v ref = 2.5v, 1 lsb = 610v 0.75 1.5 lsb differential linearity error 0.5 1 lsb offset error 0.5 6 lsb offset error match 1 0.2 1 lsb gain error 1 6 lsb gain error match 1 0.2 1 lsb power supply rejection 1 mv dynamic performance throughput frequency 50 khz conversion time 6.67 s ac accuracy thd total harmonic distortion 2 v in = 2.5v p-p @ 10khz -75 db signal-to-noise ratio v in = 2.5v p-p @ 10khz 72 db signal-to-noise (+ distortion) ratio v in = 2.5v p-p @ 10khz 69.5 db spurious-free dynamic range v in = 2.5v p-p @ 10khz 75 db voltage reference output range 2.475 2.5 2.525 v internal referenc e drift 30 ppm/oc output impedance 30 quiescent current 440 a voltage reference input range 1 v dd v input resistance 1 g reference input current pd = 01 internal ref. off, adc on @ 50ksps 4a
www.austriamicrosystems.com revision 1.03 5 - 20 AS1538/as1540 data sheet - electrical characteristics timing characteristics +v dd = + 2.7 to 5.25v, t amb = -40 to +85 oc (unless otherwise specified). all values referenced to v ihmin and v ilmax levels. cmos digital i/o v ih input high logic level +v dd x 0.7 +v dd + 0.5 v v il input low logic level -0.3 +v dd x 0.3 v v ol output low logic level 3ma sink current 0.4 v i ih input high leakage current v ih = +v dd 1a i il input low leakage current v il = gnd -1 a data format straight binary power supply requirements +v dd power supply voltage specified performance 2.7 5.25 v i qstat analog current in static mode, 3.6v pd = 00 full power-down 0.04 1.2 a pd = 01 internal ref. off, adc on 400 500 pd = 10 internal ref. on, adc off 500 600 pd = 11 internal ref. on, adc on 800 900 analog current in static mode, 5.25v pd = 00 full power-down 0.04 1.5 a pd = 01 internal ref. off, adc on 450 550 pd = 10 internal ref. on, adc off 550 650 pd = 11 internal ref. on, adc on 850 950 i q quiescent current at full speed, 3.6v pd = 01 internal ref. off, adc on 500 600 a pd = 11 internal ref. on, adc on 850 950 quiescent current at full speed, 5.25v pd = 01 internal ref. off, adc on 650 800 a pd = 11 internal ref. on, adc on 915 1150 1. guaranteed by design and characterized on sample base. 2. thd measure out to 5th harmonic. table 4. timing characteristics symbol parameter condition min typ max unit f scl scl frequency 0.1 3.4 mhz t buf bus free time between stop and start conditions 1.3 s t holdstart hold time for repeated start condition 160 ns t low scl low period 50 75 ns t high scl high period 50 75 ns t setupstart setup time for repeated start condition 100 ns t setupdata data setup time 10 ns t holddata data hold time 70 ns t risesclk 1 scl rise time 10 40 ns t risesclk1 1 scl rise time after repeated start condition and after an ack bit 10 80 ns table 3. electrical characteristics symbol parameter condition min typ max unit
www.austriamicrosystems.com revision 1.03 6 - 20 AS1538/as1540 data sheet - electrical characteristics figure 3. timing diagram t fallsclk 1 scl fall time 10 40 ns t risesda 1 sda fall time 20 80 ns t fallsda 1 sda fall time 20 80 ns t setupstop stop condition setup time 160 ns 1. guaranteed by design and characterized on sample base. table 4. timing characteristics symbol parameter condition min typ max unit repeated start sda scl start stop t buf t low t holdstart t holddata t r t high t f t setupdata t holdstart t spikesup t setupstop t setupstart
www.austriamicrosystems.com revision 1.03 7 - 20 AS1538/as1540 data sheet - typical operating characteristics 7 typical operating characteristics v dd = 3.6v; v ref = 2.5v (internal), f scl = 3.4mhz, c ref = 4.7f, t amb = +25oc (unless otherwise specified). figure 4. dnl vs. digital output co de, int. reference figure 5. inl vs. digital output code, int. reference figure 6. dnl vs. digital output co de, ext. reference figure 7. inl vs. digital output code, ext. reference figure 8. offset error vs. temperature figure 9. offset matching vs. temperature -1.2 -0.8 -0.4 0 0.4 0.8 1.2 0 1024 2048 3072 4096 digital output code inl (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 digital output code dnl (lsb) . f sample = 50ksps f sample = 50ksps -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 digital output code dnl (lsb) . f sample = 50ksps -1.2 -0.8 -0.4 0 0.4 0.8 1.2 0 1024 2048 3072 4096 digital output code inl (lsb) . f sample = 50ksps -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) offset (lsb) . -6 -4 -2 0 2 4 6 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) offset (lsb) .
www.austriamicrosystems.com revision 1.03 8 - 20 AS1538/as1540 data sheet - typical operating characteristics figure 10. offset error vs. supply voltage figure 11. offset matching vs. supply voltage figure 12. gain error vs. temperature figure 13. gain matching vs. temperature figure 14. gain error vs. supply voltage figure 15. gain matching vs. supply voltage -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) offset error (lsb) . -6 -4 -2 0 2 4 6 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) offset error (lsb) . -6 -4 -2 0 2 4 6 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) gain error (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) gain error (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) gain error (lsb) . -6 -4 -2 0 2 4 6 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) gain error (lsb) .
www.austriamicrosystems.com revision 1.03 9 - 20 AS1538/as1540 data sheet - typical operating characteristics figure 16. supply current vs. suppl y voltage, pd=00 figure 17. supply current vs. supply voltage, pd=01 figure 18. supply current vs. suppl y voltage, pd=11 figure 19. supply current vs. sampling rate, pd = 11 figure 20. fft, int. reference figure 21. fft, ext. reference 0 50 100 150 200 250 300 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) supply current (na) . 0 200 400 600 800 1000 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) supply current (a) . 0 200 400 600 800 1000 1200 0 1020304050 sampling rate (ksps) supply current (a) . 0 200 400 600 800 1000 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) supply current (a) . -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 5000 10000 15000 20000 25000 input signal frequency (khz) fft (dbc) . -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 5000 10000 15000 20000 25000 input signal frequency (khz) fft (dbc) . f sample = 50ksps n fft = 32768 snr=72.7db thd = -74.3db sfdr = 76.3db f sample = 50ksps n fft = 32768 snr=72.7db thd = -74.7db sfdr = 76.5db
www.austriamicrosystems.co m revision 1.03 10 - 20 AS1538/as1540 data sheet - detailed description 8 detailed description the AS1538/as1540 successive approximation register (sar) a/d converter architecture is based on capacitive redistribution which inherently includes a sample-and- hold function. the AS1538/as1540 core is controlled by an internally gen erated free-running clock. when the device is not perform- ing conversions or being addressed, the a/d converter-core and internal clock are powered off. figure 22. simplified i/o diagram analog input when the converter enters the hold mo de, the voltage on the selected ch x pin is captured on the internal capacitor array. the input current on the analog inputs depends on the conversion rate of the device. during the sample period, the source must charge the internal sampling capacitor (typ ically 15pf). after the capacitor has been fully charged, there is no further input current. the amou nt of charge transfer from the analog s ource to the converter is a function of conversion rate. figure 23. reference circuit AS1538/ as1540 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ref in/out gnd a0 scl sda a1 com microcontroller 0.1 to 10f 2k +2.7 to +5.25v + v dd 0.1 to 10f + 1f AS1538 only AS1538 ch0:ch7 ref in/out sda 0.1 to 10f 2k +2.7 to +5.25v + v dd 1f 10 1nf - + vin
www.austriamicrosystems.co m revision 1.03 11 - 20 AS1538/as1540 data sheet - detailed description reference voltage the AS1538/as1540 can operate with an internal 2.5v reference or an external reference. if a +5v supply is used, an external +5v reference is required in order to provide full dynamic range for a 0v to +v dd analog input. the external reference can be as low as 1v. when using a +2.7v supply, the internal +2.5v reference will provide full dynamic range for a 0v to +2.5v analog input. as the reference voltage is reduced, the analog voltage weig ht of each digital output code is reduced. this is often referred to as the lsb (least significant bit) size and is equa l to the reference voltage divided by 4096. this means that any offset or gain error inherent in the a/d converter will appear to increase, in terms of lsb size, as the reference volt- age is reduced. digital interface the AS1538/as1540 supports the i 2 c serial bus and data transmission protocol in high-speed mode at 3.4mhz. the AS1538/as1540 operates as a slave on the i 2 c bus. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. connections to the bus are made via the open-drain i/o pins scl and sda. figure 24. bus protocol the bus protocol (as shown in figure 24 ) is defined as: - data transfer may be initiated only when the bus is not busy. - during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. the bus conditions are defined as: - bus not busy . data and clock lines remain high. - start data transfer . a change in the state of the data line, from hi gh to low, while the clock is high, defines a start condition. - stop data transfe r. a change in the state of the data line, fr om low to high, while the clock line is high, defines the stop condition. - data valid . the state of the data line represents valid data, wh en, after a start condition, the data line is stable for the duration of the high period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop cond ition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth-bit. within the i 2 c bus specifications a high-speed mode (3.4mhz clock rate) is defined. - acknowledge : each receiving device, when addressed, is obliged to generate an acknowledge after the recep- tion of each byte. the master device mu st generate an extra clock pulse that is associated with this acknowledge sda scl slave address r/w direction bit start 1 2 6 7 8 9 1 23-8 8 9 ack msb repeat if more bytes transferred stop or repeated start ack from receiver ack from receiver ack
www.austriamicrosystems.co m revision 1.03 12 - 20 AS1538/as1540 data sheet - detailed description bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this ca se, the slave must leave the data line high to enable the master to generate the stop condition. figure 24 on page 11 details how data transfer is accomplished on the i 2 c bus. depending upon the state of the r/w bit, two types of data transfer are possible: - master transmitter to slave receiver . the first byte transmitted by the master is the slave address, followed by a number of data bytes. the slave returns an acknowled ge bit after the slave address and each received byte. - slave transmitter to master receiver . the first byte, the slave address, is transmitted by the master. the slave then returns an acknowledge bit. next, a number of data bytes are transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last by te. at the end of the last received byte, a not-acknowledge is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the AS1538 can operate in the following slave modes: - slave receiver mode . serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditio ns are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. - slave transmitter mode . the first byte (the slave address) is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the AS1538 while the serial clo ck is input on scl. start and stop conditions are rec- ognized as the beginning and end of a serial transfer. address byte the address byte (see figure 25) is the first byte received following the start condition from the master device. figure 25. address byte - the first five bits (msbs) of the sl ave address are factory-set to 10010. - the next two bits of the address byte are the device select bits, a1 and a0, which are set by the state of pins a1 and a0 at startup. a maximum of fo ur devices with the same pre-set code can therefore be connected on the same bus at one time. pins a1/a0 can be connected to +v dd or digital ground. - the last bit of the address byte (r/w ) define the operation to be performed. when set to a 1 a read operation is selected; when set to a 0 a write operation is selected. following the start condition, the AS1538 monitors the sda bus, checking the device type identifier being transmit- ted. upon receiving the 10010 code, the ap propriate device select bits, and the r/w bit, the slave device outputs an acknowledge signal on the sda line. command byte the AS1538/as1540 operation, including powerdown (see table 5) and channel selection (see table 6) is determined by a command byte (see figure 26) . figure 26. command byte 1 0 0 1 0 a1 a0 r/w msb654321lsb sd c2 c1 c0 pd1 pd0 x x msb654321lsb
www.austriamicrosystems.co m revision 1.03 13 - 20 AS1538/as1540 data sheet - detailed description where: sd: single-ended/differential inputs 0: differential inputs 1: single-ended inputs c2, c1, c0: channel selections pd1, pd0: power-down selection x: unused powerdown selection powerdown modes for the AS1538/as1540 are selected by setting bits pd0 and pd1 of a command byte (see com- mand byte on page 12) . channel selection channel selection for the AS1538/as1540 is made using a command byte (see command byte on page 12) . table 5. powerdown mode bit settings pd1 pd0 description 0 0 powerdown between a/d converter conversions. 0 1 internal reference off and a/d converter on. 1 0 internal reference on and a/d converter off. 1 1 internal reference on and a/d converter on. table 6. channel selection bit settings 1 1. for the 4-channel as1540 only combinations of ch0:ch3 applies. sd c2 c1 c0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 0000+in?in ------- 0001 - -+in?in ----- AS1538 only 0 0 1 0 - - - - +in ?in - - - 0 0 1 1 - - - - - - +in ?in - 0100?in+in ------- 0101 - -?in+in ----- AS1538 only 0 1 1 0 - - - - ?in +in - - - 0 1 1 1 - - - - - - ?in +in - 1000+in -------?in 1001 - -+in -----?in AS1538 only 1 0 1 0 - - - - +in - - - ?in 1 0 1 1 - - - - - - +in - ?in 1100 -+in ------ ?in 1101 - - -+in ----?in AS1538 only 1 1 1 0 - - - - - +in - - ?in 1 1 1 1 - - - - - - - +in ?in
www.austriamicrosystems.co m revision 1.03 14 - 20 AS1538/as1540 data sheet - application information 9 application information initiating a conversion after the AS1538/as1540 has been write-ad dressed by the bus master, the a/d c onverter circuitry is powered on, and conversions will begin when a command byte bit c0 (see command byte on page 12) is received. if the address byte is valid, the AS1538/as1540 will return an ack. reading data data can be read from the AS1538/as1540 by read-addr essing the device (lsb of address byte set to 1 (see com- mand byte on page 12) ) and receiving the transmitted bytes. conver ted data can only be read from the AS1538/ as1540 once a conversion has been initiated as described in initiating a conversion . each 12-bit data word (see figure 27) is returned in two bytes, where d11 is the msb of the data word, and d0 is the lsb. byte 0 is sent first, followed by byte 1. figure 27. data word figure 28 illustrates the interaction between t he master and the slave AS1538/as1540. the most efficient way to perform continuous conversions is to issue repeated starts to the AS1538/as1540 (to secure the bus for subsequent adc conversions) after r eading each conversion. it is recommended that during the conversion mode no data is clocked into the adc to prevent internal noise. therefore, after the repeated start com- mend it is recommanded not to clock in or out any data from the converter for 3.7s. the adc powers up after the pd0 bit is clocked in and it takes 1.4s to fully power up. at a cl ock frequency of 3.4mhz this ti me is automatically achieved and no extra delay should be included. figure 28. read sequence where: a: acknowledge (sda low) n: not acknowledge (sda high) s: start condition p: stop condition sr: repeated start condition w : 0 (write) r: 1 (read) 0 0 0 0 d11 d10 d9 d8 msb654321lsb d7 d6 d5 d4 d3 d2 d1 d0 byte 0 byte 1 s 1 0 0 1 0 a1 a0 w sd c2 c1 c0 pd1 pd0 x x a a sr 1 0 0 1 0 a1 a0 0 0 0 0 d11 d10 d9 d8 a a r d7 d0 n p d6 ... d1 from master to slave from slave to master adc powerdown mode adc sampling mode write-addressing byte command byte adc conversion mode read-addressing byte adc powerdown mode * * dependant on powerdown selection bits pd0 and pd1 use repeated starts to secure the bus operation and loop back to the stage of write-addressing for the next conversion. sampling instance 3.7s
www.austriamicrosystems.co m revision 1.03 15 - 20 AS1538/as1540 data sheet - application information reading with internal reference on/off the internal reference defaults to off when the AS1538/as1540 power is on. if the reference (internal or external) is continuously turned on and off, a proper amount of settli ng time must be added before a normal conversion cycle can be started. the exact amount of settling time needed varies depending on the reference capacitor. for example for a reference capacitor of 4.7f and considering the output impedance of the internal reference of 30 and the amount of time to fully charge the capacitor will be 1.4ms. if the refe rence capacitor is not fully discharged this time can be reduced greatly. figure 29 shows the correct internal reference enable sequence before issuing the typical read sequences required for the mode when an internal reference is used. note: typical read sequences can be re-used once the internal reference has settled. figure 29. internal reference enable sequence and typical read sequence where: a: acknowledge (sda low) n: not acknowledge (sda high) s: start condition p: stop condition sr: repeated start condition w : 0 (write) r: 1 (read) x: dont care s 1 0 0 1 0 a1 a0 w x x x x 1 x x x a a write-addressing byte command byte internal-reference enable sequence p wait until required settling time reached from master to slave from slave to master internal-reference enable settling time sr 1 0 0 1 0 a1 a0 w sd c2 c1 c0 1 pd0 x x a a write-addressing byte command byte adc powerdown mode adc sampling mode 0 0 0 0 d11 d10 d9 d8 d7 a d0 n p d6 ... d1 sr 1 0 0 1 0 a1 a0 r a adc conversion mode adc powerdown mode * read-addressing byte 2 x (8-bits +ack/nack settled internal reference typical mode read sequence ** * dependant on powerdown selection bits pd0 and pd1. ** to remain in hs mode, use repeated starts instead of stops settled internal reference sampling instance
www.austriamicrosystems.co m revision 1.03 16 - 20 AS1538/as1540 data sheet - application information when using the internal reference: 1. bit pd1 off the command byte must always be set to lo gic 1 for each sample conversion that is issued by the sequence, as shown in figure 28 on page 14 . 2. in order to achieve 12-bit accuracy conversion when us ing the internal reference, the internal reference set- tling time must be considered. if bit pd1 has been set to logic 0 while using the AS1538 /as1540, then the settling time must be reconsidered after pd1 is set to logic 1 (i.e., whenever the internal re ference is turned on after it has been turned off, the set- tling time must be long enough to get 12-bit accuracy conversion). 3. when the internal reference is off, it is not turned on until both the first command by te with pd1 = 1 is sent and then a stop condition or repeated start condition is i ssued. (the actual turn-on ti me occurs once the stop or repeated start condition is issued.) any command byte with pd1 = 1 issued after the internal reference is turned on serves only to keep the internal reference on. otherwise, the internal reference would be turned off by any command byte with pd1 = 0. the example in figure 29 can be generalized for a conversion cycle by simply swapping the timing of the conversion cycle. note: if an external reference is used, pd1 must be set to 0, and the external reference must be settled. the typical sequence in figure 28 on page 14 or figure 29 on page 15 can then be used. layout for optimum performance, care should be taken with the ph ysical layout of the AS1538/ as1540 circuitry. the basic sar architecture is sensitive to glitches or sudden chan ges on the power supply, refere nce, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. theref ore, during any single conver- sion for an n -bit sar converter, there are n windows in which large external transient voltages can easily affect the conversion result. such glitches might originate from swit ching power supplies, nearby digital logic, and high-power devices. - power to the AS1538/as1540 should be clean and well-bypassed. a 0.1f ceramic bypass capacitor should be placed as close to the device as possible. a 1 to 10f capacitor may also be needed if the impedance of the con- nection between +v dd and the power supply is high. - the AS1538/as1540 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. this is of particular concern when the reference input is tied to the power supply. any noise and ripple from the supply will appear directly in the digital results. - while high-frequency noise can be filtered out, voltage variation due to line frequency (50 or 60hz) can be difficult to remove. - the gnd pin should be connected to a clean ground point. in many cases, this will be the analog ground. avoid connections that are too near the grounding point of a microcontroller or digital signal processor. - the ideal layout will include an analog ground plane dedi cated to the converter and associated analog circuitry. note: for additional information download the ev aluation board applicatio n note on our website.
www.austriamicrosystems.co m revision 1.03 17 - 20 AS1538/as1540 data sheet - pack age drawings and markings 10 package drawings and markings figure 30. tssop-16 package symbol min typ max notes a--1.101,2 a1 0.05 - 0.15 1,2 a2 0.85 0.90 0.95 1,2 l 0.50 0.60 0.75 1,2 r0.09- -1,2 r1 0.09 - - 1,2 b 0.19 - 0.30 1,2,5 b1 0.19 0.22 0.25 1,2 c 0.09 - 0.20 1,2 c1 0.09 - 0.16 1,2 1 0o - 8o 1,2 l1 1.0ref 1,2 aaa 0.10 1,2 bbb 0.10 1,2 ccc 0.05 1,2 ddd 0.20 1,2 e 0.65bsc 1,2 212oref1,2 312oref1,2 variations d 4.90 5.00 5.10 1,2,3,8 e1 4.30 4.40 4.50 1,2,4,8 e 6.4bsc 1,2 e 0.65bsc 1,2 n 16 1,2,6 notes: 1. all dimensions are in millimeters; angles in degrees. 2. dimensioning and tolerancing per asme y14.5m ? 1994 . 3. dimension d does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, and gate burrs shall not exceed 0.15mm per side. 4. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusions shall not exceed 0.25mm per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. 6. terminal numbers are for reference only. 7. datums a and b to be determined at datum plane h. 8. dimensions d and e1 are to be determined at datum plane h. 9. this dimension applies only to variations with an even number of leads per side. 10. cross section a-a to be determined at 0.10 to 0.25mm from the leadtip.
www.austriamicrosystems.co m revision 1.03 18 - 20 AS1538/as1540 data sheet - pack age drawings and markings figure 31. tqfn 4x4 16-pin package notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters, angle is in degrees. 3. n is the total number of terminals. 4. terminal #1 identifier and terminal numbering conventi on shall conform to jesd 95 -1 spp-012. details of ter- minal #1 identifier are optional, but must be located within the area indi cated. the terminal #1 identifier may be either a mold, embedded metal or mark feature. 5. dimension b applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. 6. nd refers to the maximum number of terminals on d side. 7. unilateral coplanarity zone applies to the ex posed heat sink slug as well as the terminals. symbol min typ max notes a 0.70 0.75 0.80 1, 2 a1 0.00 0.02 0.05 1, 2 l 0.45 0.55 0.65 1, 2 l1 0.03 0.15 1, 2 k0.20 1, 2 aaa0.101, 2 bbb0.101, 2 ccc 0.10 1, 2 ddd0.051, 2 symbol min typ max notes d bsc 4.00 1, 2 e bsc 4.00 1, 2 d2 2.00 2.15 2.25 1, 2 e2 2.00 2.15 2.25 1, 2 b 0.25 0.30 0.35 1, 2, 5 e0.65 n161, 2 nd 4 1, 2, 5
www.austriamicrosystems.co m revision 1.03 19 - 20 AS1538/as1540 data sheet - ordering information 11 ordering information the device is available as the standard products shown in table 7 . table 7. ordering information model marking description delivery form package AS1538-btst AS1538 8-channel, 12-bit i2c analog- to-digital converter tape and reel tssop-16 AS1538-btsu AS1538 8-channel, 12-bit i2c anal og-to-digital converter tubes tssop-16 as1540-bqft as1540 4-channel, 12-bit i2c analog-to-digital converter tape and reel tqfn 4x4 16-pin
www.austriamicrosystems.co m revision 1.03 20 - 20 AS1538/as1540 data sheet copyrights copyright ? 1997-200 7, austriamicrosystems ag, schloss premstaett en, 8141 unterpremstae tten, austria-europe. trademarks registered ?. all rights reserved. the materi al herein may not be reprodu ced, adapted, merged, trans- lated, stored, or used witho ut the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austria- microsystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a syst em, it is necessary to check with aust riamicrosystems ag for current informa- tion. this product is intended for use in normal commercial applications. applications requiring extend ed temperature range, unusual environmental requirements, or high reliability app lications, such as military, medical life-support or life- sustaining equipment are specifically not recommended wit hout additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the m anufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or ar ising out of the furnishing, performance or use of the tech- nical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag a-8141 schloss premstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors a nd representatives, please visit: http://www.austriamicrosystems.com/contact

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